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» Register renaming and dynamic speculation: an alternative ap...
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ICS
1999
Tsinghua U.
13 years 10 months ago
Classifying load and store instructions for memory renaming
Memory operations remain a significant bottleneck in dynamically scheduled pipelined processors, due in part to the inability to statically determine the existence of memory addr...
Glenn Reinman, Brad Calder, Dean M. Tullsen, Gary ...
ARVLSI
1999
IEEE
112views VLSI» more  ARVLSI 1999»
13 years 10 months ago
Architectural Considerations for Application-Specific Counterflow Pipelines
Application-specific processor design is a promising approach for meeting the performance and cost goals of a system. Application-specific processors are especially promising for ...
Bruce R. Childers, Jack W. Davidson
IEEEPACT
2005
IEEE
13 years 12 months ago
Compiler Directed Early Register Release
This paper presents a novel compiler directed technique to reduce the register pressure and power of the register file by releasing registers early. The compiler identifies regi...
Timothy M. Jones, Michael F. P. O'Boyle, Jaume Abe...
EUROMICRO
1999
IEEE
13 years 10 months ago
Delft-Java Dynamic Translation
This paper describes the DELFT-JAVA processor and the mechanisms required to dynamically translate JVM instructions into DELFT-JAVA instructions. Using a form of hardware register...
C. John Glossner, Stamatis Vassiliadis
ISCA
2008
IEEE
185views Hardware» more  ISCA 2008»
13 years 6 months ago
From Speculation to Security: Practical and Efficient Information Flow Tracking Using Speculative Hardware
Dynamic information flow tracking (also known as taint tracking) is an appealing approach to combat various security attacks. However, the performance of applications can severely...
Haibo Chen, Xi Wu, Liwei Yuan, Binyu Zang, Pen-Chu...