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ISSS
2002
IEEE
127views Hardware» more  ISSS 2002»
15 years 4 months ago
Dynamic Common Sub-Expression Elimination during Scheduling in High-Level Synthesis
We introduce a new approach, “Dynamic Common Sub-expression Elimination (CSE)”, that dynamically eliminates common sub- expressions based on new opportunities created during s...
Alexandru Nicolau, Nikil D. Dutt, Rajesh Gupta, Ni...
HIPEAC
2009
Springer
15 years 3 months ago
HeDGE: Hybrid Dataflow Graph Execution in the Issue Logic
Abstract. Exposing more instruction-level parallelism in out-of-order superscalar processors requires increasing the number of dynamic in-flight instructions. However, large instru...
Suriya Subramanian, Kathryn S. McKinley
CC
1998
Springer
111views System Software» more  CC 1998»
14 years 11 months ago
Live Range Splitting in a Graph Coloring Register Allocator
Graph coloring is the dominant paradigm for global register allocation [8, 7, 4]. Coloring allocators use an interference graph, Z, to model conflicts that prevent two values from ...
Keith D. Cooper, L. Taylor Simpson
INFOCOM
1999
IEEE
15 years 3 months ago
Enhancing Survivability of Mobile Internet Access Using Mobile IP with Location Registers
The Mobile IP (MIP) protocol for IP version 4 provides continuous Internet connectivity to mobile hosts. However, currently it has some drawbacks in the areas of survivability, per...
Ravi Jain, Thomas Raleigh, Danny Yang, Li-Fung Cha...
ISCA
2003
IEEE
150views Hardware» more  ISCA 2003»
15 years 5 months ago
Cyclone: A Broadcast-Free Dynamic Instruction Scheduler with Selective Replay
To achieve high instruction throughput, instruction schedulers must be capable of producing high-quality schedules that maximize functional unit utilization while at the same time...
Dan Ernst, Andrew Hamel, Todd M. Austin