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VLSID
2004
IEEE
138views VLSI» more  VLSID 2004»
16 years 2 months ago
Synthesis-driven Exploration of Pipelined Embedded Processors
Recent advances on language based software toolkit generation enables performance driven exploration of embedded systems by exploiting the application behavior. There is a need fo...
Prabhat Mishra, Arun Kejariwal, Nikil Dutt
SAMOS
2004
Springer
15 years 7 months ago
Self-loop Pipelining and Reconfigurable Dataflow Arrays
Abstract. This paper presents some interesting concepts of static dataflow machines that can be used by reconfigurable computing architectures. We introduce some data-driven reconf...
João M. P. Cardoso
ICWS
2009
IEEE
14 years 11 months ago
Web Service Mashup Middleware with Partitioning of XML Pipelines
Traditionally, the composition of Web services to create mashups has been achieved by using an application server as a mediator between a client browser and services. To avoid thi...
Eric Wohlstadter, Peng Li, Brett Cannon
HPCA
1996
IEEE
15 years 6 months ago
Co-Scheduling Hardware and Software Pipelines
Exploiting instruction-level parallelism (ILP) is extremely important for achieving high performance in application specific instruction set processors (ASIPs) and embedded process...
Ramaswamy Govindarajan, Erik R. Altman, Guang R. G...
ICCAD
2001
IEEE
128views Hardware» more  ICCAD 2001»
15 years 10 months ago
An Assembly-Level Execution-Time Model for Pipelined Architectures
The aim of this work is to provide an elegant and accurate static execution timing model for 32-bit microprocessor instruction sets, covering also inter–instruction effects. Suc...
Giovanni Beltrame, Carlo Brandolese, William Forna...