407 search results - page 29 / 82 » Register-Sensitive Software Pipelining |
VLSI
2010
Springer
15 years 9 days ago
2010
Springer
—Latency insensitivity is a promising design paradigm in the nanometer era since it has potential benefits of increased modularity and robustness to variations. Synchronous elas...
120
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WCET
2010
14 years 11 months ago
2010
Safe and tight worst-case execution times (WCETs) are important when scheduling hard realtime systems. This paper presents METAMOC, a modular method, based on model checking and s...
113
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CASES
2001
ACM
15 years 5 months ago
2001
ACM
Current development tools for embedded real-time systems do not efficiently support the timing aspect. The most important timing parameter for scheduling and system analysis is th...
111
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FCCM
2000
IEEE
15 years 6 months ago
2000
IEEE
Hardware compilation techniques which use highlevel programming languages to describe and synthesize hardware are gaining popularity. They are especially useful for reconfigurable...
114
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CODES
2008
IEEE
15 years 3 months ago
2008
IEEE
Functional validation is a major bottleneck in microprocessor design methodology. Simulation is the widely used method for functional validation using billions of random and biase...