407 search results - page 32 / 82 » Register-Sensitive Software Pipelining |
118
click to vote
WSCG
2004
15 years 3 months ago
2004
The paper specifies modular software for synchronous and asynchronous computer-mediated communication and visualization in network-distributed environments. It is new because the ...
DAC
1999
ACM
16 years 2 months ago
1999
ACM
Abstract { This paper presents the machine description language LISA for the generation of bitand cycle accurate models of DSP processors. Based on a behavioral operation descripti...
109
Voted
CODES
2006
IEEE
15 years 8 months ago
2006
IEEE
Heteregenous multiprocessor SoCs are becoming a reality, largely due to the abundance of transistors, intellectual property cores and powerful design tools. In this project, we ex...
EUROMICRO
1999
IEEE
15 years 6 months ago
1999
IEEE
This paper describes the DELFT-JAVA processor and the mechanisms required to dynamically translate JVM instructions into DELFT-JAVA instructions. Using a form of hardware register...
ICIP
2007
IEEE
16 years 3 months ago
2007
IEEE
The in-loop deblocking filter contains highly adaptive processing on both sample level and block edge level, which inevitably appears in the loop kernel of the algorithm. Therefor...