407 search results - page 64 / 82 » Register-Sensitive Software Pipelining |
121
Voted
PPOPP
2010
ACM
15 years 8 months ago
2010
ACM
In processors with several levels of hardware resource sharing, like CMPs in which each core is an SMT, the scheduling process becomes more complex than in processors with a singl...
124
click to vote
MICRO
2007
IEEE
15 years 8 months ago
2007
IEEE
Recently, the microprocessor industry has moved toward chip multiprocessor (CMP) designs as a means of utilizing the increasing transistor counts in the face of physical and micro...
123
click to vote
ACSC
2006
IEEE
15 years 8 months ago
2006
IEEE
Interactive virtual reality requires at least 60 frames per second in order to ensure smooth motion. For a good immersive experience, it is also necessary to have low end-to-end l...
112
click to vote
DATE
2006
IEEE
15 years 8 months ago
2006
IEEE
Cutting-edge applications of future embedded systems demand highest processor performance with low power consumption to get acceptable battery-life times. Therefore, low power opt...
125
click to vote
IEEEPACT
2006
IEEE
15 years 8 months ago
2006
IEEE
This paper describes a compiler for stream programs that efficiently schedules computational kernels and stream memory operations, and allocates on-chip storage. Our compiler uses...