407 search results - page 70 / 82 » Register-Sensitive Software Pipelining |
128
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CGO
2004
IEEE
15 years 5 months ago
2004
IEEE
Instruction scheduling hardware can be simplified and easily pipelined if pairs of dependent instructions are fused so they share a single instruction scheduling slot. We study an...
129
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CASES
2006
ACM
15 years 5 months ago
2006
ACM
Ever increasing performance requirements have elevated deeply pipelined architectures to a standard even in the embedded processor domain, requiring the incorporation of dynamic b...
111
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DICS
2006
15 years 5 months ago
2006
Dynamic Parallel Schedules (DPS) is a flow graph based framework for developing parallel applications on clusters of workstations. The DPS flow graph execution model enables automa...
107
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EDBTW
2006
Springer
15 years 5 months ago
2006
Springer
Abstract. Algorithms for processing Structural Joins embody essential building blocks for XML query evaluation. Their design is a difficult task, because they have to satisfy many ...
142
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EMSOFT
2006
Springer
15 years 5 months ago
2006
Springer
Concurrent programming languages should be a good fit for embedded systems because they match the intrinsic parallelism of their architectures and environments. Unfortunately, typ...