407 search results - page 73 / 82 » Register-Sensitive Software Pipelining |
126
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GLVLSI
1998
IEEE
15 years 6 months ago
1998
IEEE
With the increased clock frequency of modern, high-performance processors over 500 MHz, in some cases, limiting the power dissipation has become the most stringent design target. ...
138
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TACAS
1998
Springer
15 years 6 months ago
1998
Springer
This paper enables symbolic ternary simulation of systems with large embedded memories. Each memory array is replaced with a behavioral model, where the number of symbolic variable...
96
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ASPDAC
2007
ACM
15 years 5 months ago
2007
ACM
- TOSHIBA has developed mobile multi-media engine SoC, we call as S1G, which can realize low power ISDB-T one-segment decode in 42mW for eight months short period of time. Since MP...
131
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CHES
2003
Springer
15 years 5 months ago
2003
Springer
Abstract. Performance evaluation of the Advanced Encryption Standard candidates has led to intensive study of both hardware and software implementations. However, although plentifu...
111
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ISHPC
2000
Springer
15 years 5 months ago
2000
Springer
Deeply pipelined high performance processors require highly accurate branch prediction to drive their instruction fetch. However there remains a class of events which are not easi...