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WADT
2001
Springer
15 years 3 months ago
Verifying a Simple Pipelined Microprocessor Using Maude
Abstract. We consider the verification of a simple pipelined microprocessor in Maude, by implementing an equational theoretical model of systems. Maude is an equationally-based la...
Neal A. Harman
ISPASS
2006
IEEE
15 years 5 months ago
Characterizing the branch misprediction penalty
Despite years of study, branch mispredictions remain as a significant performance impediment in pipelined superscalar processors. In general, the branch misprediction penalty can...
Stijn Eyerman, James E. Smith, Lieven Eeckhout
FPL
2004
Springer
95views Hardware» more  FPL 2004»
15 years 4 months ago
Solving SAT with a Context-Switching Virtual Clause Pipeline and an FPGA Embedded Processor
Abstract. This paper proposes an architecture that combines a contextswitching virtual configware/software SAT solver with an embedded processor to promote a tighter coupling betwe...
C. J. Tavares, C. Bungardean, G. M. Matos, Jos&eac...
ICASSP
2011
IEEE
14 years 2 months ago
A fully automated 2-DE gel image analysis pipeline for high throughput proteomics
Image analysis is still considered as the bottleneck in 2D-gel based expression proteomics analysis for biomarkers discovery. We are presenting a new end-to-end image analysis pip...
Panagiotis Tsakanikas, Elias S. Manolakos
VISUALIZATION
2005
IEEE
15 years 4 months ago
The Visible Radio: Process Visualization of a Software-Defined Radio
In this case study, a data-oriented approach is used to visualize a complex digital signal processing pipeline. The pipeline implements a Frequency Modulated (FM) Software-Defined...
Matthew Hall, Alex Betts, Donna Cox, David Pointer...