This paper proposes a formal verification methodology which is smoothly integrated with component-based system-level design, using a divide and conquer approach. The methodology a...
In this paper we demonstrate a potential extension of formal verification methodology in order to deal with time-domain properties of analog and mixed-signal circuits whose dynamic...
A key problem for effective unit testing is the difficulty of partitioning large software systems into appropriate units that can be tested in isolation. We present an approach th...
Behrmann et al. posed the question whether "To Store or Not To Store" [1] states during reachability analysis, in order to counter the effects of the well-known state spa...
Recently, a new approach to the symbolic model checking of timed automata based on a partial order semantics was introduced, which relies on event zones that use vectors of event o...