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ASYNC
2007
IEEE
129views Hardware» more  ASYNC 2007»
15 years 9 months ago
Formal Verification of CHP Specifications with CADP Illustration on an Asynchronous Network-on-Chip
Few formal verification techniques are currently available for asynchronous designs. In this paper, we describe a new approach for the formal verification of asynchronous architec...
Gwen Salaün, Wendelin Serwe, Yvain Thonnart, ...
138
Voted
DASFAA
2004
IEEE
92views Database» more  DASFAA 2004»
15 years 8 months ago
Modeling Temporally Variable Transportation Networks
In this paper, a State-Based Dynamic Transportation Network (SBDTN) model is presented, which can be used to describe the spatiotemporal aspect of temporally variable transportatio...
Zhiming Ding, Ralf Hartmut Güting
160
Voted
COMPGEOM
2001
ACM
15 years 8 months ago
Computing a 3-dimensional cell in an arrangement of quadrics: exactly and actually!
We present two approaches to the problem of calculating a cell in a 3-dimensional arrangement of quadrics. The first approach solves the problem using rational arithmetic. It work...
Nicola Geismann, Michael Hemmer, Elmar Schöme...
160
Voted
TAPSOFT
1995
Springer
15 years 8 months ago
Static and Dynamic Processor Allocation for Higher-Order Concurrent Languages
Starting from the process algebra for Concurrent ML we develop two program analyses that facilitate the intelligent placement of processes on processors. Both analyses are obtaine...
Hanne Riis Nielson, Flemming Nielson
CTRSA
2008
Springer
160views Cryptology» more  CTRSA 2008»
15 years 6 months ago
Fault Analysis Study of IDEA
We present a study of several fault attacks against the block cipher IDEA. Such a study is particularly interesting because of the target cipher's specific property to employ ...
Christophe Clavier, Benedikt Gierlichs, Ingrid Ver...