1179 search results - page 11 / 236 » Relative Timing Based Verification of Timed Circuits and Sys... |
VLSI
2007
Springer
15 years 3 months ago
2007
Springer
— Software simulation remains the most used method for VHDL RTL functional verification. The functional verification process essentially consists of two parts. The first one is t...
JIRS
2007
14 years 9 months ago
2007
A detailed step-by-step approach is presented to optimize, standardize, and automate the process of unmanned vehicle controller design, evaluation, validation and verification, fol...
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RTSS
1999
IEEE
15 years 1 months ago
1999
IEEE
In this paper we present improved techniques for the schedulability analysis of tasks with precedence relations in multiprocessor and distributed systems, scheduled under a preemp...
ESORICS
2006
Springer
15 years 1 months ago
2006
Springer
Timing side channels are a serious threat to the security of cryptographic algorithms. This paper presents a novel method for the timing-sensitive analysis of information flow in s...
VLDB
1987
ACM
15 years 29 days ago
1987
ACM
A model for a historical database is described which is based upon time-stamped tuples as the unit of storage. The model includes both physical and logical time-stamps. The techni...