1179 search results - page 14 / 236 » Relative Timing Based Verification of Timed Circuits and Sys... |
ISSTA
1998
ACM
15 years 1 months ago
1998
ACM
We present various techniques for improving the time and space efficiency of symbolic model checking for system requirements specified as synchronous finite state machines. We use...
88
Voted
ENTCS
2006
14 years 9 months ago
2006
Patterns for property specification enable non-experts to write formal specifications that can be used for automatic model checking. The existing patterns identified in [6] allow ...
EURODAC
1994
IEEE
15 years 1 months ago
1994
IEEE
Due to the complexity of today's systems, prototyping by simulation must be based on simulation-engine-like performance. It is proved by implementations that compiler-driven ...
DAC
2000
ACM
15 years 10 months ago
2000
ACM
We recently introduced symbolic timing simulation (STS) using data-dependent delays as a tool for verifying the timing of fullcustom transistor-level circuit designs, and for the ...
RTAS
2007
IEEE
15 years 3 months ago
2007
IEEE
Discrete-event (DE) models are formal system specifications that have analyzable deterministic behaviors. Using a global, consistent notion of time, DE components communicate via...