Sciweavers

1179 search results - page 15 / 236
» Relative Timing Based Verification of Timed Circuits and Sys...
Sort
View
CGF
2006
132views more  CGF 2006»
14 years 9 months ago
Verification of Physically Based Rendering Algorithms
Within computer graphics, the field of predictive rendering is concerned with those methods of image synthesis which yield results that do not only look real, but are also radiome...
Christiane Ulbricht, Alexander Wilkie, Werner Purg...
FPGA
2005
ACM
215views FPGA» more  FPGA 2005»
15 years 3 months ago
Design, layout and verification of an FPGA using automated tools
Creating a new FPGA is a challenging undertaking because of the significant effort that must be spent on circuit design, layout and verification. It currently takes approximately ...
Ian Kuon, Aaron Egier, Jonathan Rose
FORMATS
2007
Springer
15 years 1 months ago
Partial Order Reduction for Verification of Real-Time Components
Abstract. We describe a partial order reduction technique for a realtime component model. Components are described as timed automata with data ports, which can be composed in stati...
John Håkansson, Paul Pettersson
87
Voted
TVLSI
2002
130views more  TVLSI 2002»
14 years 9 months ago
Incremental compilation for parallel logic verification systems
Although simulation remains an important part of application-specific integrated circuit (ASIC) validation, hardware-assisted parallel verification is becoming a larger part of the...
R. Tessier, S. Jana
76
Voted
ETFA
2006
IEEE
15 years 3 months ago
A Framework for Fault Tolerant Real Time Systems Based on Reconfigurable FPGAs
♦ To increase the amount of logic available to the users in SRAM-based FPGAs, manufacturers are using nanometric technologies to boost logic density and reduce costs, making its ...
Manuel G. Gericota, Luís F. Lemos, Gustavo ...