Sciweavers

1179 search results - page 18 / 236
» Relative Timing Based Verification of Timed Circuits and Sys...
Sort
View
PR
2006
145views more  PR 2006»
14 years 9 months ago
Gait recognition using linear time normalization
We present a novel system for gait recognition. Identity recognition and verification are based on the matching of linearly timenormalized gait walking cycles. A novel feature ext...
Nikolaos V. Boulgouris, Konstantinos N. Platanioti...
EURODAC
1994
IEEE
141views VHDL» more  EURODAC 1994»
15 years 1 months ago
Exact path sensitization in timing analysis
of a direct implementation of this criterion. This paper presents the first critical path finding tool based on the exact criterion. It offers therefore better results in compariso...
R. Peset Llopis
74
Voted
EMSOFT
2008
Springer
14 years 11 months ago
Automatically transforming and relating Uppaal models of embedded systems
Relations between models are important for effective automatic validation, for comparing implementations with specifications, and for increased understanding of embedded systems d...
Timothy Bourke, Arcot Sowmya
DAC
2002
ACM
15 years 10 months ago
A solenoidal basis method for efficient inductance extraction
The ability to compute the parasitic inductance of the interconnect is critical to the timing verification of modern VLSI circuits. A challenging aspect of inductance extraction i...
Hemant Mahawar, Vivek Sarin, Weiping Shi
ISQED
2002
IEEE
175views Hardware» more  ISQED 2002»
15 years 2 months ago
On the Relation between SAT and BDDs for Equivalence Checking
State-of-the-art verification tools are based on efficient operations on Boolean formulas. Traditional manipulation techniques are based on Binary Decision Diagrams (BDDs) and SAT...
Sherief Reda, Rolf Drechsler, Alex Orailoglu