1179 search results - page 26 / 236 » Relative Timing Based Verification of Timed Circuits and Sys... |
110
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DFG
2004
Springer
15 years 3 months ago
2004
Springer
This paper presents the real-time model checker RAVEN and related theoretical background. RAVEN augments the efficiency of traditional symbolic model checking with possibilities to...
ICCAD
2005
IEEE
15 years 8 months ago
2005
IEEE
— Variability in the chip design process has been relatively increasing with technology scaling to smaller dimensions. Using worst case analysis for circuit optimization severely...
FPL
2000
Springer
15 years 3 months ago
2000
Springer
This paper reports on a method for extending existing VHDL design and verification software available for the Xilinx Virtex series of FPGAs. It allows the designer to apply standa...
121
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NIPS
2003
15 years 1 months ago
2003
A mixed-signal image filtering VLSI has been developed aiming at real-time generation of edge-based image vectors for robust image recognition. A four-stage asynchronous median de...
AMAST
2006
Springer
15 years 3 months ago
2006
Springer
Abstract. When designing an open system, there might be no implementation available for certain components at verification time. For such systems, verification has to be based on a...