1179 search results - page 34 / 236 » Relative Timing Based Verification of Timed Circuits and Sys... |
115
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FDL
2003
IEEE
15 years 5 months ago
2003
IEEE
Reconfigurable Systolic Arrays are a generalization of Systolic Arrays where node operations and interconnections can be redefined even at run time. This flexibility increases the...
ISCAS
2005
IEEE
15 years 5 months ago
2005
IEEE
Abstract— The analysis of effects induced by interconnects become increasingly important as the scale of process technologies steadily shrinks. While most analyses focus on the t...
CAV
2001
Springer
15 years 3 months ago
2001
Springer
In this paper we present the application of generalized retiming for temporal property checking. Retiming is a structural transformation that relocates registers in a circuit-based...
108
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DATE
2010
IEEE
15 years 4 months ago
2010
IEEE
—We present a new technique for statistical static timing analysis (SSTA) based on Markov chain Monte Carlo (MCMC), that allows fast and accurate estimation of the right-hand tai...
110
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SIBGRAPI
2000
IEEE
15 years 4 months ago
2000
IEEE
This work has as main objective to present an off-line signature verification system. It is basically divided into three parts. The first one demonstrates a pre-processing process,...