Sciweavers

239 search results - page 42 / 48
» Relative debugging for a highly parallel hybrid computer sys...
Sort
View
ICCD
2006
IEEE
128views Hardware» more  ICCD 2006»
15 years 6 months ago
Polaris: A System-Level Roadmap for On-Chip Interconnection Networks
Technology trends are driving parallel on-chip architectures in the form of multi-processor systems-on-a-chip (MPSoCs) and chip multi-processors (CMPs). In these systems the incre...
Vassos Soteriou, Noel Eisley, Hangsheng Wang, Bin ...
EDCC
2006
Springer
15 years 1 months ago
SEU Mitigation Techniques for Microprocessor Control Logic
The importance of fault tolerance at the processor architecture level has been made increasingly important due to rapid advancements in the design and usage of high performance de...
T. S. Ganesh, Viswanathan Subramanian, Arun K. Som...
PDIS
1994
IEEE
15 years 1 months ago
Achieving Transaction Scaleup on Unix
Constructing scalable high-performance applications on commodity hardware running the Unix operating system is a problem that must be addressed in several application domains. We ...
Marie-Anne Neimat, Donovan A. Schneider
CF
2006
ACM
15 years 3 months ago
Exploiting locality to ameliorate packet queue contention and serialization
Packet processing systems maintain high throughput despite relatively high memory latencies by exploiting the coarse-grained parallelism available between packets. In particular, ...
Sailesh Kumar, John Maschmeyer, Patrick Crowley
CCGRID
2008
IEEE
15 years 4 months ago
A Proactive Non-Cooperative Game-Theoretic Framework for Data Replication in Data Grids
— Data grids and its cost effective nature has taken on a new level of interest in recent years; amalgamation of different providers results in increased capacity as well as lowe...
Ali Elghirani, Riky Subrata, Albert Y. Zomaya