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NN
2006
Springer
14 years 9 months ago
Speed-accuracy trade-off in planned arm movements with delayed feedback
The Vector Integration to Endpoint (VITE) circuit describes a real-time neural network model simulating behavioral and neurobiological properties of planned arm and hand movements...
Dan Beamish, I. Scott MacKenzie, Jianhong Wu
ASPDAC
2007
ACM
116views Hardware» more  ASPDAC 2007»
15 years 1 months ago
Safe Delay Optimization for Physical Synthesis
-- Physical synthesis is a relatively young field in Electronic Design Automation. Many published optimizations for physical synthesis end up hurting the final result, often by neg...
Kai-Hui Chang, Igor L. Markov, Valeria Bertacco
ISQED
2003
IEEE
116views Hardware» more  ISQED 2003»
15 years 3 months ago
Analyzing Statistical Timing Behavior of Coupled Interconnects Using Quadratic Delay Change Characteristics
With continuing scaling of CMOS process, process variations in the form of die-to-die and within-die variations become significant which cause timing uncertainty. This paper prop...
Tom Chen, Amjad Hajjar
VLSID
2002
IEEE
160views VLSI» more  VLSID 2002»
15 years 10 months ago
PREDICTMOS MOSFET Model and its Application to Submicron CMOS Inverter Delay Analysis
Predictive delay analysis is presented for a representative CMOS inverter with submicron device size using PREDICTMOS MOSFET model. As against SPICE, which adopts a time consuming...
A. B. Bhattacharyya, Shrutin Ulman
ICN
2001
Springer
15 years 2 months ago
A Buffer-Management Scheme for Bandwidth and Delay Differentiation Using a Virtual Scheduler
—This paper presents a new scalable buffer-management scheme for IP Differentiated Services. The scheme consists of a Differentiated Random Drop (DRD) algorithm using feedback fr...
Roman Pletka, Patrick Droz, Burkhard Stiller