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ICCAD
2005
IEEE
176views Hardware» more  ICCAD 2005»
15 years 8 months ago
Statistical gate sizing for timing yield optimization
— Variability in the chip design process has been relatively increasing with technology scaling to smaller dimensions. Using worst case analysis for circuit optimization severely...
Debjit Sinha, Narendra V. Shenoy, Hai Zhou
COMSWARE
2007
IEEE
15 years 6 months ago
Impact of Network Dynamics on Tardiness of Data in Sensor Networks
- Impact of random delays and losses in sensor networks manifests in the form of tardiness of data used for processing at the sink nodes. The age of data used by the end applicatio...
Tarun Banka, Anura P. Jayasumana
GLVLSI
2006
IEEE
185views VLSI» more  GLVLSI 2006»
15 years 6 months ago
Application of fast SOCP based statistical sizing in the microprocessor design flow
In this paper we have applied statistical sizing in an industrial setting. Efficient implementation of the statistical sizing algorithm is achieved by utilizing a dedicated interi...
Murari Mani, Mahesh Sharma, Michael Orshansky
VTC
2006
IEEE
159views Communications» more  VTC 2006»
15 years 5 months ago
Comparison between Vertical Handoff Decision Algorithms for Heterogeneous Wireless Networks
— The next generation wireless networks will support the vertical handoff mechanism in which users can maintain the connections when they switch from one network to another (e.g....
Enrique Stevens-Navarro, Vincent W. S. Wong
ADHOCNOW
2005
Springer
15 years 5 months ago
Reed-Solomon and Hermitian Code-Based Scheduling Protocols for Wireless Ad Hoc Networks
Abstract. In this work we investigate bounds on throughput and delay performance of a scheduling protocol that derives its decisions from codes traditionally used to correct or det...
Carlos H. Rentel, Thomas Kunz