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ICCAD
2009
IEEE
179views Hardware» more  ICCAD 2009»
13 years 4 months ago
Automatic memory partitioning and scheduling for throughput and power optimization
Hardware acceleration is crucial in modern embedded system design to meet the explosive demands on performance and cost. Selected computation kernels for acceleration are usually ...
Jason Cong, Wei Jiang, Bin Liu, Yi Zou
DATE
2002
IEEE
105views Hardware» more  DATE 2002»
13 years 11 months ago
Power-Manageable Scheduling Technique for Control Dominated High-Level Synthesis
Optimizing power consumption at high-level is a critical step towards power-efficient digital system designs. This paper addresses the power management problem by scheduling a giv...
Chunhong Chen, Majid Sarrafzadeh
DATE
2008
IEEE
116views Hardware» more  DATE 2008»
14 years 26 days ago
A Variation Aware High Level Synthesis Framework
— The worst-case delay/power of function units has been used in traditional high level synthesis to facilitate design space exploration. As technology scales to nanometer regime,...
Feng Wang 0004, Guangyu Sun, Yuan Xie
ICCD
2006
IEEE
126views Hardware» more  ICCD 2006»
14 years 3 months ago
Task Merging for Dynamic Power Management of Cyclic Applications in Real-Time Multi-Processor Systems
—In this paper we propose the method of task merging and idle period clustering for dynamic power management (DPM) in a real-time system with multiple processing elements. We sho...
Shaobo Liu, Qinru Qiu, Qing Wu
RTS
2008
119views more  RTS 2008»
13 years 5 months ago
Symbolic quality control for multimedia applications
We present a fine grain quality control method for multimedia applications. The method takes as input an application software composed of actions. The execution times of actions a...
Jacques Combaz, Jean-Claude Fernandez, Joseph Sifa...