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ISLPED
2005
ACM
111views Hardware» more  ISLPED 2005»
15 years 8 months ago
Peak temperature control and leakage reduction during binding in high level synthesis
Temperature is becoming a first rate design criterion in ASICs due to its negative impact on leakage power, reliability, performance, and packaging cost. Incorporating awareness o...
Rajarshi Mukherjee, Seda Ogrenci Memik, Gokhan Mem...
CAIP
2005
Springer
194views Image Analysis» more  CAIP 2005»
15 years 8 months ago
Comparative Study of 3D Face Acquisition Techniques
Today, communication devices are evolving towards friendly–user interactivity while permanently eyeing towards 3D display technologies. As such, 3D face generation, modelling an...
Mark Chan, Patrice Delmas, Georgy L. Gimel'farb, P...
ASPDAC
2004
ACM
126views Hardware» more  ASPDAC 2004»
15 years 7 months ago
High-level area and power-up current estimation considering rich cell library
— Reducing the ever-growing leakage power is critical to power efficient designs. Leakage reduction techniques such as power-gating using sleep transistor insertion introduces la...
Fei Li, Lei He, Joseph M. Basile, Rakesh J. Patel,...
CODES
2003
IEEE
15 years 7 months ago
Schedule-aware performance estimation of communication architecture for efficient design space exploration
In this paper, we are concerned about the performance estimation of bus-based architectures assuming that the task partitioning on the processing components is already determined....
Sungchan Kim, Chaeseok Im, Soonhoi Ha
ISLPED
2003
ACM
100views Hardware» more  ISLPED 2003»
15 years 7 months ago
Checkpointing alternatives for high performance, power-aware processors
High performance processors use checkpointing to rapidly recover from branch mispredictions and possibly other exceptions. We demonstrate that conventional checkpointing becomes u...
Andreas Moshovos