Sciweavers

37 search results - page 3 / 8
» Reliability evaluation of combinational logic circuits by sy...
Sort
View
GLVLSI
2010
IEEE
156views VLSI» more  GLVLSI 2010»
13 years 11 months ago
A multi-level approach to reduce the impact of NBTI on processor functional units
NBTI is one of the most important silicon reliability problems facing processor designers today. The impact of NBTI can be mitigated at both the circuit and microarchitecture leve...
Taniya Siddiqua, Sudhanva Gurumurthi
ISQED
2009
IEEE
126views Hardware» more  ISQED 2009»
14 years 1 months ago
Robust differential asynchronous nanoelectronic circuits
Abstract — Nanoelectronic design faces unprecedented reliability challenges and must achieve noise immunity and delay insensitiveness in the presence of prevalent defects and sig...
Bao Liu
DATE
2006
IEEE
141views Hardware» more  DATE 2006»
14 years 8 days ago
Evaluating coverage of error detection logic for soft errors using formal methods
—In this paper we describe a methodology to measure exactly the quality of fault-tolerant designs by combining faultinjection in high level design (HLD) descriptions with a forma...
Udo Krautz, Matthias Pflanz, Christian Jacobi 0002...
JOLPE
2010
97views more  JOLPE 2010»
13 years 4 months ago
Low-Power Soft Error Hardened Latch
This paper presents a low-power soft error-hardened latch suitable for reliable circuit operation. The proposed circuit uses redundant feedback loop to protect latch against soft e...
Hossein Karimiyan Alidash, Vojin G. Oklobdzija
TPHOL
1999
IEEE
13 years 10 months ago
Lifted-FL: A Pragmatic Implementation of Combined Model Checking and Theorem Proving
Combining theorem proving and model checking o ers the tantalizing possibility of e ciently reasoning about large circuits at high levels of abstraction. We have constructed a syst...
Mark Aagaard, Robert B. Jones, Carl-Johan H. Seger