282 search results - page 17 / 57 » Reliability- and process-variation aware design of integrate... |
134
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GLVLSI
2010
IEEE
15 years 6 months ago
2010
IEEE
Graphene nanoribbon tunneling FETs (GNR TFETs) are promising devices for post-CMOS low-power applications because of the low subthreshold swing, high Ion/Ioff, and potential for l...
115
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FTEDA
2007
15 years 1 months ago
2007
The number of gates on a chip is quickly growing toward and beyond the one billion mark. Keeping all the gates running at the beat of a single or a few rationally related clocks i...
110
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DAC
2005
ACM
16 years 2 months ago
2005
ACM
We present an efficient optimization scheme for gate sizing in the presence of process variations. Using a posynomial delay model, the delay constraints are modified to incorporat...
ICCD
2004
IEEE
15 years 10 months ago
2004
IEEE
Abstract - This paper describes a communicationcentric design methodology that addresses the fundamental challenges induced by the emergence of truly heterogeneous Systems-on-Chip ...
119
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DAC
2004
ACM
15 years 5 months ago
2004
ACM
The high leakage current in nano-meter regimes is becoming a significant portion of power dissipation in CMOS circuits as threshold voltage, channel length, and gate oxide thickne...