525 search results - page 77 / 105 » Reliability-Based Design Optimization of Robotic System Dyna... |
IPCCC
2006
IEEE
15 years 3 months ago
2006
IEEE
Low power has been considered as an important issue in instruction cache (I-cache) designs. Several studies have shown that the I-cache can be tuned to reduce power. These techniq...
MICRO
2003
IEEE
15 years 2 months ago
2003
IEEE
This paper proposes and evaluates single-ISA heterogeneous multi-core architectures as a mechanism to reduce processor power dissipation. Our design incorporates heterogeneous cor...
93
Voted
JSAC
2011
14 years 4 months ago
2011
— The growing interest in vehicular ad hoc networks (VANETs) enables decentralized traveler information systems to become more feasible and effective in Intelligent Transportatio...
DAC
2007
ACM
15 years 10 months ago
2007
ACM
This paper presents a variation resilient circuit design technique for maintaining parametric yield of design under inherent variation in process parameters. We propose to utilize...
ICCAD
2009
IEEE
14 years 7 months ago
2009
IEEE
Multi-core processors have become an integral part of mainstream high performance computer systems. In parallel, exponentially increasing power density and packaging costs have ne...