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» Reliability-Centric High-Level Synthesis
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RSP
2005
IEEE
164views Control Systems» more  RSP 2005»
15 years 3 months ago
High Level Synthesis for Data-Driven Applications
Abstract— John von Neumann proposed his famous architecture in a context where hardware was very expensive and bulky. His goal was to maximize functionality with minimal hardware...
Etienne Bergeron, Xavier Saint-Mleux, Marc Feeley,...
ISLPED
2005
ACM
111views Hardware» more  ISLPED 2005»
15 years 3 months ago
Peak temperature control and leakage reduction during binding in high level synthesis
Temperature is becoming a first rate design criterion in ASICs due to its negative impact on leakage power, reliability, performance, and packaging cost. Incorporating awareness o...
Rajarshi Mukherjee, Seda Ogrenci Memik, Gokhan Mem...
ISQED
2007
IEEE
162views Hardware» more  ISQED 2007»
15 years 3 months ago
Balanced Scheduling and Operation Chaining in High-Level Synthesis for FPGA Designs
In high-level synthesis for FPGA designs, scheduling and chaining of operations for optimal performance remain challenging problems. In this paper, we present a balanced schedulin...
David Zaretsky, Gaurav Mittal, Robert P. Dick, Pri...
IESS
2007
Springer
128views Hardware» more  IESS 2007»
15 years 3 months ago
An Interactive Design Environment for C-based High-Level Synthesis
: Much effort in RTL design has been devoted to developing “push-button” types of tools. However, given the highly complex nature, and lack of control on RTL design, push-butt...
Dongwan Shin, Andreas Gerstlauer, Rainer Döme...
ISQED
2005
IEEE
81views Hardware» more  ISQED 2005»
15 years 3 months ago
An ILP Formulation for Reliability-Oriented High-Level Synthesis
Reliability decisions taken early in system design can bring significant benefits in terms of design quality. This paper presents a 0-1 integer linear programming (ILP) formulatio...
Suleyman Tosun, Ozcan Ozturk, Nazanin Mansouri, Er...