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» Reliability-Centric High-Level Synthesis
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150
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DATE
2003
IEEE
137views Hardware» more  DATE 2003»
15 years 9 months ago
Dynamic Conditional Branch Balancing during the High-Level Synthesis of Control-Intensive Designs
We present two novel strategies to increase the scope for application of speculative code motions: (1) Adding scheduling steps dynamically during scheduling to conditional branche...
Sumit Gupta, Nikil D. Dutt, Rajesh K. Gupta, Alexa...
151
Voted
ISSS
2000
IEEE
127views Hardware» more  ISSS 2000»
15 years 8 months ago
Lower Bound Estimation for Low Power High-Level Synthesis
This paper addresses the problem of estimating lower bounds on the power consumption in scheduled data flow graphs with a fixed number of allocated resources prior to binding. T...
Lars Kruse, Eike Schmidt, Gerd Jochens, Ansgar Sta...
138
Voted
VLSID
2009
IEEE
155views VLSI» more  VLSID 2009»
16 years 4 months ago
Unified Challenges in Nano-CMOS High-Level Synthesis
: The challenges in nano-CMOS circuit design include the following: variability, leakage, power, thermals, reliability, and yield. This talk will focus on interdependent considerat...
Saraju P. Mohanty
134
Voted
ISSS
2002
IEEE
127views Hardware» more  ISSS 2002»
15 years 8 months ago
Dynamic Common Sub-Expression Elimination during Scheduling in High-Level Synthesis
We introduce a new approach, “Dynamic Common Sub-expression Elimination (CSE)”, that dynamically eliminates common sub- expressions based on new opportunities created during s...
Alexandru Nicolau, Nikil D. Dutt, Rajesh Gupta, Ni...
95
Voted
VLSID
2001
IEEE
82views VLSI» more  VLSID 2001»
16 years 4 months ago
High Level Synthesis Of Multi-Precision Data Flow Graphs
Vikas Agrawal, Anand Pande, Mahesh Mehendale