174 search results - page 15 / 35 » Reliability-Centric High-Level Synthesis |
115
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GLVLSI
2000
IEEE
15 years 4 months ago
2000
IEEE
In this paper we present a novel and fast estimation technique that produces tight latency lower bounds for Data Flow Graphs representing time critical segments of the application...
ICCAD
2000
IEEE
15 years 4 months ago
2000
IEEE
100
Voted
ICCD
2001
IEEE
15 years 9 months ago
2001
IEEE
In this paper, we present a high-level power modeling technique to estimate the power consumption of reconfigurable devices such as complex programmable logic devices (CPLDs) and ...
122
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EVOW
2001
Springer
15 years 5 months ago
2001
Springer
The integrated circuits design flow is rapidly moving towards higher description levels. However, test-related activities are lacking behind this trend, mainly since effective faul...
110
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IPPS
2006
IEEE
15 years 6 months ago
2006
IEEE
Current electronic system design requires to be concerned with power consumption consideration. However, in a lot of design tools, the application power consumption budget is esti...