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ISCAS
2003
IEEE
96views Hardware» more  ISCAS 2003»
15 years 5 months ago
A novel improvement technique for high-level test synthesis
Improving testability during the early stages of High-Level Synthesis (HLS) has several benefits, including reduced test hardware overhead, reduced test costs, reduced design iter...
Saeed Safari, Hadi Esmaeilzadeh, Amir-Hossein Jaha...
DATE
2006
IEEE
127views Hardware» more  DATE 2006»
15 years 6 months ago
ASIP design and synthesis for non linear filtering in image processing
This paper presents an Application Specific Instruction Set Processor (ASIP) design for the implementation of a class of nonlinear image processing algorithms, the Retinex-like fi...
Luca Fanucci, Michele Cassiano, Sergio Saponara, D...
TSD
2004
Springer
15 years 5 months ago
Slovak Text-to-Speech Synthesis in ARTIC System
Abstract. This paper presents a brand-new Slovak text-to-speech system. It was developed within the framework of ARTIC system (primarily designed to synthesize Czech speech) with r...
Jindrich Matousek, Daniel Tihelka
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ISCAS
2007
IEEE
141views Hardware» more  ISCAS 2007»
15 years 6 months ago
Towards a GBit/s Programmable Decoder for LDPC Convolutional Codes
Abstract— We analyze the decoding algorithm for regular timeinvariant LDPC convolutional codes as a 3D signal processing scheme and derive several parallelization concepts, which...
Emil Matús, Marcos B. S. Tavares, Marcel Bi...
ISLPED
2003
ACM
96views Hardware» more  ISLPED 2003»
15 years 5 months ago
Effective graph theoretic techniques for the generalized low power binding problem
This paper proposes two very fast graph theoretic heuristics for the low power binding problem given fixed number of resources and multiple architectures for the resources. First...
Azadeh Davoodi, Ankur Srivastava