174 search results - page 9 / 35 » Reliability-Centric High-Level Synthesis |
105
Voted
DAC
1994
ACM
15 years 7 months ago
1994
ACM
This paper introduces hot potato high level synthesis transformation techniques. These techniques add deflection operations in a computation in such a way that a specific goal is ...
112
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ISSS
2002
IEEE
15 years 8 months ago
2002
IEEE
In existing synthesis systems, the influence of the area and delay of the controller is not or not sufficiently taken into account. But the controller can have a big influence,...
142
Voted
VLSID
2003
IEEE
16 years 3 months ago
2003
IEEE
The design of modern complex embedded systems require a high level of abstraction of the design. The SimnML[1] is a specification language to model processors for such designs. Se...
121
Voted
ICCAD
2003
IEEE
16 years 12 days ago
2003
IEEE
This work is a contribution to high level synthesis for low power systems. While device feature size decreases, interconnect power becomes a dominating factor. Thus it is importan...
129
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DATE
2007
IEEE
15 years 9 months ago
2007
IEEE
Loop unrolling is a well-known compiler optimization that can lead to significant performance improvements. When used in High Level Synthesis (HLS) unrolling can affect the contr...