Sciweavers

1311 search results - page 189 / 263
» Remarks on Hardware Implementation of Image Processing Algor...
Sort
View
ITC
2002
IEEE
81views Hardware» more  ITC 2002»
15 years 8 months ago
Design Rewiring Using ATPG
—Logic optimization is the step of the very large scale integration (VLSI) design cycle where the designer performs modifications on a design to satisfy different constraints suc...
Andreas G. Veneris, Magdy S. Abadir, Mandana Amiri
ECBS
2003
IEEE
145views Hardware» more  ECBS 2003»
15 years 8 months ago
Model Checking and Evidence Exploration
We present an algebraic framework for evidence exploration: the process of interpreting, manipulating, and navigating the proof structure or evidence produced by a model checker w...
Yifei Dong, C. R. Ramakrishnan, Scott A. Smolka
ICCD
1994
IEEE
142views Hardware» more  ICCD 1994»
15 years 7 months ago
Grammar-Based Optimization of Synthesis Scenarios
Systems for multi-level logic optimization are usually based on a set of specialized, loosely-related transformations which work on a network representation. The sequence of trans...
Andreas Kuehlmann, Lukas P. P. P. van Ginneken
ISCAS
1994
IEEE
104views Hardware» more  ISCAS 1994»
15 years 7 months ago
Stereo Correspondence with Discrete-Time Cellular Neural Networks
In this paper, we propose a new approach of solving the stereopsis problem with a discrete-time cellular neural network(DTCNN) where each node has connectionsonly with its local n...
Sungjun Park, Seung-Jai Min, Soo-Ik Chae
139
Voted
ICVS
1999
Springer
15 years 7 months ago
Ascender II, a Visual Framework for 3D Reconstruction
This paper presents interim results from an ongoing project on aerial image reconstruction. One important task in image interpretation is the process of understanding and identifyi...
Maurício Marengoni, Christopher O. Jaynes, ...