1311 search results - page 54 / 263 » Remarks on Hardware Implementation of Image Processing Algor... |
64
Voted
VLSISP
2002
14 years 10 months ago
2002
Multi-valued and universal binary neurons (MVN and UBN) are the neural processing elements with the complex-valued weights and high functionality. It is possible to implement an a...
80
Voted
DFT
2003
IEEE
15 years 3 months ago
2003
IEEE
The implementation of imaging arrays for System-On-a-Chip (SOC) is aided by using faulttolerant light sensors. Fault-tolerant redundancy in an Active Pixel Sensor (APS) is obtaine...
79
Voted
DATE
2009
IEEE
15 years 5 months ago
2009
IEEE
—FPGAs are widely used for evaluating the error-floor performance of LDPC (low-density parity check) codes. We propose a scalable vector decoder for FPGA-based implementation of...
73
Voted
DATE
2000
IEEE
15 years 2 months ago
2000
IEEE
This paper presents a single chip implementation of a space-time algorithm for co-channel interference (CCI) and intersymbol interference (ISI) reduction in GSM/DCS systems. The t...
78
Voted
EUROGP
2001
Springer
15 years 2 months ago
2001
Springer
This paper describes how animat-based “food foraging” techniques may be applied to the design of low-level image processing algorithms. First, we show how we implemented the fo...