74 search results - page 14 / 15 » Reordering Algorithm for Minimizing Test Power in VLSI Circu... |
ISPD
2009
ACM
14 years 1 months ago
2009
ACM
The multiple-supply voltage (MSV) design style has been extensively applied to mitigate dynamic-power consumption. The MSV design paradigm, however, brings many crucial challenges...
FPGA
2003
ACM
13 years 11 months ago
2003
ACM
This paper presents a new power saving, high speed FPGA design enhancing a previous SiGe CML FPGA based on the Xilinx 6200 FPGA. The design aims at having a higher performance but...
ISQED
2007
IEEE
14 years 15 days ago
2007
IEEE
In nanometer regime, the effects of variations are having an increasing impact on the delay and power characteristics of devices as well as the yield of the circuit. Statistical t...
ISQED
2008
IEEE
14 years 18 days ago
2008
IEEE
In this paper dual-K (DKCMOS) technology is proposed as a method for gate leakage power reduction. An integer linear programming (ILP) based algorithm is proposed for its optimiza...
FPGA
2006
ACM
13 years 10 months ago
2006
ACM
Embedded memory blocks are important resources in contemporary FPGA devices. When targeting FPGAs, application designers often specify high-level memory functions which exhibit a ...