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ISPD
2009
ACM
112views Hardware» more  ISPD 2009»
14 years 1 months ago
Post-floorplanning power/ground ring synthesis for multiple-supply-voltage designs
The multiple-supply voltage (MSV) design style has been extensively applied to mitigate dynamic-power consumption. The MSV design paradigm, however, brings many crucial challenges...
Wan-Ping Lee, Diana Marculescu, Yao-Wen Chang
FPGA
2003
ACM
167views FPGA» more  FPGA 2003»
13 years 11 months ago
A scalable 2 V, 20 GHz FPGA using SiGe HBT BiCMOS technology
This paper presents a new power saving, high speed FPGA design enhancing a previous SiGe CML FPGA based on the Xilinx 6200 FPGA. The design aims at having a higher performance but...
Jong-Ru Guo, Chao You, Kuan Zhou, Bryan S. Goda, R...
ISQED
2007
IEEE
152views Hardware» more  ISQED 2007»
14 years 15 days ago
Variation Aware Timing Based Placement Using Fuzzy Programming
In nanometer regime, the effects of variations are having an increasing impact on the delay and power characteristics of devices as well as the yield of the circuit. Statistical t...
Venkataraman Mahalingam, N. Ranganathan
ISQED
2008
IEEE
153views Hardware» more  ISQED 2008»
14 years 18 days ago
ILP Based Gate Leakage Optimization Using DKCMOS Library during RTL Synthesis
In this paper dual-K (DKCMOS) technology is proposed as a method for gate leakage power reduction. An integer linear programming (ILP) based algorithm is proposed for its optimiza...
Saraju P. Mohanty
FPGA
2006
ACM
129views FPGA» more  FPGA 2006»
13 years 10 months ago
Power-aware RAM mapping for FPGA embedded memory blocks
Embedded memory blocks are important resources in contemporary FPGA devices. When targeting FPGAs, application designers often specify high-level memory functions which exhibit a ...
Russell Tessier, Vaughn Betz, David Neto, Thiagara...