Sciweavers

454 search results - page 19 / 91
» Representation results for defeasible logic
Sort
View
89
Voted
IOLTS
2008
IEEE
83views Hardware» more  IOLTS 2008»
15 years 7 months ago
On the Minimization of Potential Transient Errors and SER in Logic Circuits Using SPFD
Sets of Pairs of Functions to be Distinguished (SPFD) is a functional flexibility representation method that was recently introduced in the logic synthesis domain, and promises s...
Sobeeh Almukhaizim, Yiorgos Makris, Yu-Shen Yang, ...
151
Voted
DAC
2006
ACM
16 years 1 months ago
Symmetry detection for large Boolean functions using circuit representation, simulation, and satisfiability
- Classical two-variable symmetries play an important role in many EDA applications, ranging from logic synthesis to formal verification. This paper proposes a complete circuit-bas...
Jin S. Zhang, Alan Mishchenko, Robert K. Brayton, ...
102
Voted
ICDAR
2005
IEEE
15 years 6 months ago
Towards a Canonical and Structured Representation of PDF Documents through Reverse Engineering
This article presents Xed, a reverse engineering tool for PDF documents, which extracts the original document layout structure. Xed mixes electronic extraction methods with state-...
Maurizio Rigamonti, Jean-Luc Bloechle, Karim Hadja...
CADE
2000
Springer
15 years 4 months ago
Automated Proof Construction in Type Theory Using Resolution
We provide techniques to integrate resolution logic with equality in type theory. The results may be rendered as follows. − A clausification procedure in type theory, equipped w...
Marc Bezem, Dimitri Hendriks, Hans de Nivelle
70
Voted
FOIS
2010
15 years 1 months ago
Ontology Verification with Repositories
Abstract. In this paper we show how the relationships between first-order ontologies within a repository can be used to support ontology verification. We discuss the use of represe...
Michael Grüninger, Torsten Hahmann, Ali Hashe...