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» Representation results for defeasible logic
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85
Voted
ICCAD
1991
IEEE
100views Hardware» more  ICCAD 1991»
15 years 4 months ago
Extraction of Gate Level Models from Transistor Circuits by Four-Valued Symbolic Analysis
The program TRANALYZE generates a gate-level representation of an MOS transistor circuit. The resulting model contains only four-valued unit and zero delay logic primitives, suita...
Randal E. Bryant
EUSFLAT
2009
135views Fuzzy Logic» more  EUSFLAT 2009»
14 years 10 months ago
Image Analysis Applications of Morphological Operators based on Uninorms
This paper presents a continuation of the study on a mathematical morphology based on left-continuous conjunctive uninorms given in [1]. Experimental results are displayed using th...
Manuel González Hidalgo, Arnau Mir Torres, ...
ISMVL
1998
IEEE
109views Hardware» more  ISMVL 1998»
15 years 4 months ago
Implementing a Multiple-Valued Decision Diagram Package
Decision diagrams are the state-of-the-art representation for logic functions, both binary and multiple-valued. Here we consider issues regarding the efficient implementation of a...
D. Miller, Rolf Drechsler
78
Voted
ENTCS
2008
128views more  ENTCS 2008»
15 years 20 days ago
Algebraic Stuttering Simulations
Rewrite theories and their associated Kripke structures constitute a flexible and executable framework in which a wide range of systems can be studied. We present a general notion...
Narciso Martí-Oliet, José Meseguer, ...
112
Voted
AAAI
1996
15 years 1 months ago
Formalizing Narratives Using Nested Circumscription
The representation of narratives of actions and observations is a current issue in Knowledge Representation, where traditional plan-oriented treatments of action seem to fall shor...
Chitta Baral, Alfredo Gabaldon, Alessandro Provett...