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» Representational Reasoning and Verification
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110
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ISPW
2006
IEEE
15 years 7 months ago
Definition and Analysis of Election Processes
This paper shows that process definition and analysis technologies can be used to reason about the vulnerability of election processes with respect to incorrect or fraudulent behav...
Mohammad S. Raunak, Bin Chen, Amr Elssamadisy, Lor...
114
Voted
DSD
2005
IEEE
116views Hardware» more  DSD 2005»
15 years 6 months ago
Validation of Embedded Systems Using Formal Method Aided Simulation
This paper proposes a validation approach, based on simulation, which addresses problems related to both state space explosion of formal methods and low coverage of informal metho...
Daniel Karlsson, Petru Eles, Zebo Peng
103
Voted
UML
2001
Springer
15 years 5 months ago
A Formal Mapping between UML Static Models and Algebraic Specifications
: There are several reasons to specify UML models in a formal way The most important are to avoid inconsistencies and ambiguities and to do verification and forecasting of system p...
Liliana Favre
83
Voted
EUROMICRO
2000
IEEE
15 years 5 months ago
Formal Coverification of Embedded Systems Using Model Checking
The complexity of embedded systems is increasing rapidly. In consequence, new verification techniques that overcome the limitations of traditional methods and are suitable for har...
Luis Alejandro Cortés, Petru Eles, Zebo Pen...
APSEC
1998
IEEE
15 years 5 months ago
Verifying Model Oriented Specifications through Animation
In this paper we demonstrate how light weight tools can be used to increase the level of confidence in Z specifications. In particular we outline the Pipedream approach to explori...
Edmund Kazmierczak, Michael Winikoff, Philip W. Da...