6147 search results - page 1159 / 1230 » Requirements, Architectures and Risks |
MICRO
2006
IEEE
15 years 5 months ago
2006
IEEE
As the industry moves toward larger-scale chip multiprocessors, the need to parallelize applications grows. High inter-thread communication delays, exacerbated by over-stressed hi...
82
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MICRO
2006
IEEE
15 years 5 months ago
2006
IEEE
To protect processor logic from soft errors, multicore redundant architectures execute two copies of a program on separate cores of a chip multiprocessor (CMP). Maintaining identi...
MICRO
2006
IEEE
15 years 5 months ago
2006
IEEE
Recently-proposed processor microarchitectures for high Memory Level Parallelism (MLP) promise substantial performance gains. Unfortunately, current cache hierarchies have Miss-Ha...
107
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SBACPAD
2006
IEEE
15 years 5 months ago
2006
IEEE
Neural-inspired branch predictors achieve very low branch misprediction rates. However, previously proposed implementations have a variety of characteristics that make them challe...
ANCS
2006
ACM
15 years 5 months ago
2006
ACM
Buffered crossbar switches are a special type of crossbar switches. In such a switch, besides normal input queues and output queues, a small buffer is associated with each crosspo...