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CGO
2008
IEEE
16 years 12 hour ago
Parallel-stage decoupled software pipelining
In recent years, the microprocessor industry has embraced chip multiprocessors (CMPs), also known as multi-core architectures, as the dominant design paradigm. For existing and ne...
Easwaran Raman, Guilherme Ottoni, Arun Raman, Matt...
CISS
2008
IEEE
16 years 10 hour ago
Reconstruction of compressively sensed images via neurally plausible local competitive algorithms
Abstract—We develop neurally plausible local competitive algorithms (LCAs) for reconstructing compressively sensed images. Reconstruction requires solving a sparse approximation ...
Robert L. Ortman, Christopher J. Rozell, Don H. Jo...
CODES
2008
IEEE
16 years 9 hour ago
Online adaptive utilization control for real-time embedded multiprocessor systems
To provide Quality of Service (QoS) guarantees in open and unpredictable environments, the utilization control problem is defined to keep the processor utilization at the schedula...
Jianguo Yao, Xue Liu, Mingxuan Yuan, Zonghua Gu
CODES
2008
IEEE
16 years 9 hour ago
Static analysis of processor stall cycle aggregation
Processor Idle Cycle Aggregation (PICA) is a promising approach for low power execution of processors, in which small memory stalls are aggregated to create a large one, and the p...
Jongeun Lee, Aviral Shrivastava
DSRT
2008
IEEE
16 years 4 hour ago
Interfacing and Coordination for a DEVS Simulation Protocol Standard
The DEVS formalism has been adopted and developed independently by many research teams, which led to various DEVS implementation versions. Consequently, different DEVS implementat...
Khaldoon Al-Zoubi, Gabriel A. Wainer
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