46 search results - page 2 / 10 » Resistive bridge fault modeling, simulation and test generat... |
DATE
2006
IEEE
14 years 9 days ago
2006
IEEE
Generation of n -detection test sets is typically done for a single fault model. In this work we investigate the generation of n -detection test sets by pairing each fault of a ta...
DFT
1998
IEEE
13 years 10 months ago
1998
IEEE
ITC
1991
IEEE
13 years 9 months ago
1991
IEEE
Two approaches have been used to balance the cost of generating e ective tests for ICs and the need to increase the ICs' quality level. The rst approach favorsusing high-leve...
VTS
2005
IEEE
13 years 11 months ago
2005
IEEE
We present three resistive bridging fault models valid for different CMOS technologies. The models are partitioned into a general framework (which is shared by all three models) a...
GLVLSI
2002
IEEE
13 years 11 months ago
2002
IEEE
This paper develops new techniques for detecting both stuck-open faults and resistive open faults, which result in increased delays along some paths. The improved detection of CMO...