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61
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VLSID
2004
IEEE
89views VLSI» more  VLSID 2004»
15 years 9 months ago
Response Surface Modeling of 100nm CMOS Process Technology using Design of Experiment
H. C. Srinivasaiah, Navakanta Bhat
ISQED
2005
IEEE
125views Hardware» more  ISQED 2005»
15 years 3 months ago
A New Method for Design of Robust Digital Circuits
As technology continues to scale beyond 100nm, there is a significant increase in performance uncertainty of CMOS logic due to process and environmental variations. Traditional c...
Dinesh Patil, Sunghee Yun, Seung-Jean Kim, Alvin C...
84
Voted
ASPDAC
2007
ACM
144views Hardware» more  ASPDAC 2007»
15 years 1 months ago
Parameter Reduction for Variability Analysis by Slice Inverse Regression (SIR) Method
With semiconductor fabrication technologies scaled below 100 nm, the design-manufacturing interface becomes more and more complicated. The resultant process variability causes a nu...
Alexander V. Mitev, Michael Marefat, Dongsheng Ma,...
ISQED
2008
IEEE
101views Hardware» more  ISQED 2008»
15 years 3 months ago
Projection-Based Piecewise-Linear Response Surface Modeling for Strongly Nonlinear VLSI Performance Variations
Large-scale process fluctuations (particularly random device mismatches) at nanoscale technologies bring about highdimensional strongly nonlinear performance variations that canno...
Xin Li, Yu Cao
WSC
2001
14 years 10 months ago
Implementation of response surface methodology using variance reduction techniques in semiconductor manufacturing
Semiconductor manufacturing is generally considered a cyclic industry. As such, individual producers able to react quickly and appropriately to market conditions will have a compe...
Charles D. McAllister, Bertan Altuntas, Matthew Fr...