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» Results in Combined Route Traversal and Collision Avoidance
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TC
2008
13 years 6 months ago
Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors
The design and performance of next-generation chip multiprocessors (CMPs) will be bound by the limited amount of power that can be dissipated on a single die. We present photonic n...
Assaf Shacham, Keren Bergman, Luca P. Carloni
PAM
2005
Springer
13 years 11 months ago
A Merged Inline Measurement Method for Capacity and Available Bandwidth
— We have proposed a new TCP version, called ImTCP (Inline measurement TCP), in [1]. The ImTCP sender adjusts the transmission intervals of data packets, and then utilizes the ar...
Cao Le Thanh Man, Go Hasegawa, Masayuki Murata
ICES
2010
Springer
277views Hardware» more  ICES 2010»
13 years 4 months ago
An Efficient, High-Throughput Adaptive NoC Router for Large Scale Spiking Neural Network Hardware Implementations
Recently, a reconfigurable and biologically inspired paradigm based on network-on-chip (NoC) and spiking neural networks (SNNs) has been proposed as a new method of realising an ef...
Snaider Carrillo, Jim Harkin, Liam McDaid, Sandeep...
IMC
2009
ACM
14 years 24 days ago
Triangle inequality variations in the internet
Triangle inequality violations (TIVs) are important for latency sensitive distributed applications. On one hand, they can expose opportunities to improve network routing by findi...
Cristian Lumezanu, Randolph Baden, Neil Spring, Bo...