Ethernet line rates are projected to reach 100 Gbits/s by as soon as 2010. While in principle suitable for high performance clustered and parallel applications, Ethernet requires ...
In this paper, we address the problem of guaranteeing end-to-end (ETE) delay of packets in a distributed system where the technique of time division multiplex access (TDMA)is adop...
Memory trace analysis is an important technology for architecture research, system software (i.e., OS, compiler) optimization, and application performance improvements. Many appro...
Yungang Bao, Mingyu Chen, Yuan Ruan, Li Liu, Jianp...
The process of design search and optimisation is characterised by its computationally intensive operations, which produce a problem well suited to Grid computing. Here we present a...
Gang Xue, Matt J. Fairman, Graeme E. Pound, Simon ...
Abstract. As low-level architectural support for context-aware computing matures, we are ready to explore more general and powerful means of accessing context data. Information req...
Jeffrey Heer, Alan Newberger, Chris Beckmann, Jaso...