57 search results - page 7 / 12 » Retiming and clock scheduling for digital circuit optimizati... |
ICCAD
1994
IEEE
15 years 1 months ago
1994
IEEE
A simple extension of the critical path method is presented which allows more accurate optimization of circuits with level-sensitive latches. The extended formulation provides a s...
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DAC
1998
ACM
15 years 1 months ago
1998
ACM
We present a technique for synthesizing power- as well as area-optimized circuits from hierarchical data flow graphs under throughput constraints. We allow for the use of complex...
VLSID
1999
IEEE
15 years 1 months ago
1999
IEEE
This paper provides a theoretical basis for eliminating or reducing the energy consumption due to transients in a synchronous digital circuit. The transient energy is minimized wh...
TCAD
1998
14 years 9 months ago
1998
—This paper introduces a novel optimization paradigm for increasing the throughput of digital systems. The basic idea consists of transforming fixed-latency units into variable-...
ICCAD
2003
IEEE
15 years 6 months ago
2003
IEEE
We present a new approach for TAM optimization and test scheduling in the modular testing of mixed-signal SOCs. A test planning approach for digital SOCs is extended to handle ana...