34 search results - page 4 / 7 » Reusing Scan Chains for Test Pattern Decompression |
ICCD
2004
IEEE
15 years 6 months ago
2004
IEEE
This paper introduces a new method for deterministic diagnosis of logic cores. The proposed method is based on onchip decompression and comparison of incompletely specified test ...
63
Voted
ATS
2009
IEEE
15 years 4 months ago
2009
IEEE
Diagnosis is increasingly important, not only for individual analysis of failing ICs, but also for high-volume test response analysis which enables yield and test improvement. Sca...
71
Voted
ISQED
2010
IEEE
15 years 2 months ago
2010
IEEE
— This paper proposes a two-dimensional scan shift control concept for multiple scan chain design. Multiple scan chain test scheme provides very low scan power by skipping many l...
85
Voted
ATS
2004
IEEE
15 years 1 months ago
2004
IEEE
In this paper, we propose a low-power testing methodology for the scan-based BIST. A smoother is included in the test pattern generator (TPG) to reduce average power consumption d...
ICCAD
1997
IEEE
15 years 1 months ago
1997
IEEE
Asynchronous circuits operate correctly only under timing assumptions. Hence testing those circuits for delay faults is crucial. This paper describes a three-step method to detect...