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DATE
2003
IEEE
109views Hardware» more  DATE 2003»
15 years 9 months ago
A Novel Metric for Interconnect Architecture Performance
We propose a new metric for evaluation of interconnect architectures. This metric is computed by optimal assignment of wires from a given wire length distribution (WLD) to a given...
Parthasarathi Dasgupta, Andrew B. Kahng, Swamy Mud...
130
Voted
DFT
2003
IEEE
64views VLSI» more  DFT 2003»
15 years 9 months ago
Hybrid BIST Time Minimization for Core-Based Systems with STUMPS Architecture
1 This paper presents a solution to the test time minimization problem for core-based systems that contain sequential cores with STUMPS architecture. We assume a hybrid BIST approa...
Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, ...
DFT
2003
IEEE
113views VLSI» more  DFT 2003»
15 years 9 months ago
Buffer and Controller Minimisation for Time-Constrained Testing of System-On-Chip
Test scheduling and Test Access Mechanism (TAM) design are two important tasks in the development of a System-on-Chip (SOC) test solution. Previous test scheduling techniques assu...
Anders Larsson, Erik Larsson, Petru Eles, Zebo Pen...
HICSS
2003
IEEE
162views Biometrics» more  HICSS 2003»
15 years 9 months ago
Decision Support Models for Composing and Navigating through e-Learning Objects
Libraries of learning objects may serve as basis for deriving course offerings that are customized to the needs of different learning communities or even individuals. Several ways...
Gerhard Knolmayer
134
Voted
ICDAR
2003
IEEE
15 years 9 months ago
A Study on Top-down Word Image Generation for Handwritten Word Recognition
This paper describes a top-down word image generation model for holistic handwritten word recognition. To generate a word image, it uses likelihoods based, respectively, on a ling...
Eiki Ishidera, Daisuke Nishiwaki
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