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DSN
2006
IEEE
15 years 4 months ago
CADRE: Cycle-Accurate Deterministic Replay for Hardware Debugging
One of the main reasons for the difficulty of hardware verification is that hardware platforms are typically nondeterministic at clock-cycle granularity. Uninitialized state ele...
Smruti R. Sarangi, Brian Greskamp, Josep Torrellas
SI3D
2006
ACM
15 years 4 months ago
Hardware accelerated multi-resolution geometry synthesis
In this paper, we propose a new technique for hardware accelerated multi-resolution geometry synthesis. The level of detail for a given viewpoint is created on-the-fly, allowing f...
Martin Bokeloh, Michael Wand
EXPCS
2007
15 years 1 months ago
Empirical performance assessment using soft-core processors on reconfigurable hardware
Simulation has been the de facto standard method for performance evaluation of newly proposed ideas in computer architecture for many years. While simulation allows for theoretica...
Richard Hough, Praveen Krishnamurthy, Roger D. Cha...
EGH
2004
Springer
15 years 1 months ago
Efficient partitioning of fragment shaders for multiple-output hardware
Partitioning fragment shaders into multiple rendering passes is an effective technique for virtualizing shading resource limits in graphics hardware. The Recursive Dominator Split...
Tim Foley, Mike Houston, Pat Hanrahan
FCCM
1999
IEEE
127views VLSI» more  FCCM 1999»
15 years 2 months ago
Mapping of an Automated Target Recognition Application from a Graphical Software Environment to FPGA-Based Reconfigurable Hardwa
A significant obstacle to the widespread adoption of FPGAbased configurable computing hardware has been the difficulty of mapping applications onto this hardware. We are developin...
Benjamin A. Levine, Senthil Natarajan, Chandra Tan...