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CODES
2005
IEEE
15 years 3 months ago
Aggregating processor free time for energy reduction
Even after carefully tuning the memory characteristics to the application properties and the processor speed, during the execution of real applications there are times when the pr...
Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, ...
CODES
2005
IEEE
15 years 3 months ago
Improving superword level parallelism support in modern compilers
Multimedia vector instruction sets are becoming ubiquitous in most of the embedded systems used for multimedia, networking and communications. However, current compiler technology...
Christian Tenllado, Luis Piñuel, Manuel Pri...
IEEEPACT
2005
IEEE
15 years 3 months ago
Trace Cache Sampling Filter
This paper presents a new technique for efficient usage of small trace caches. A trace cache can significantly increase the performance of wide out-oforder processors, but to be e...
Michael Behar, Avi Mendelson, Avinoam Kolodny
IEEEPACT
2005
IEEE
15 years 3 months ago
A Distributed Control Path Architecture for VLIW Processors
VLIW architectures are popular in embedded systems because they offer high-performance processing at low cost and energy. The major problem with traditional VLIW designs is that t...
Hongtao Zhong, Kevin Fan, Scott A. Mahlke, Michael...
MSS
2005
IEEE
62views Hardware» more  MSS 2005»
15 years 3 months ago
Predictive Reduction of Power and Latency (PuRPLe)
Increasing efforts have been aimed towards the management of power as a critical system resource, and the disk can consume approximately a third of the power required for a typica...
Matthew Craven, Ahmed Amer
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