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HPCA
2008
IEEE
16 years 2 months ago
An OS-based alternative to full hardware coherence on tiled CMPs
The interconnect mechanisms (shared bus or crossbar) used in current chip-multiprocessors (CMPs) are expected to become a bottleneck that prevents these architectures from scaling...
Christian Fensch, Marcelo Cintra
105
Voted
SC
2009
ACM
15 years 9 months ago
Implementing a high-volume, low-latency market data processing system on commodity hardware using IBM middleware
A stock market data processing system that can handle high data volumes at low latencies is critical to market makers. Such systems play a critical role in algorithmic trading, ri...
Xiaolan J. Zhang, Henrique Andrade, Bugra Gedik, R...
DATE
2009
IEEE
176views Hardware» more  DATE 2009»
15 years 9 months ago
Automated synthesis of streaming C applications to process networks in hardware
Abstract—The demand for embedded computing power is continuously increasing and FPGAs are becoming very interesting computing platforms, as they provide huge amounts of customiza...
Sven van Haastregt, Bart Kienhuis
DSN
2008
IEEE
15 years 8 months ago
Using likely program invariants to detect hardware errors
In the near future, hardware is expected to become increasingly vulnerable to faults due to continuously decreasing feature size. Software-level symptoms have previously been used...
Swarup Kumar Sahoo, Man-Lap Li, Pradeep Ramachandr...
GECCO
2007
Springer
268views Optimization» more  GECCO 2007»
15 years 8 months ago
Synthesis of analog filters on an evolvable hardware platform using a genetic algorithm
This work presents a novel approach to filter synthesis on a field programmable analog array (FPAA) architecture using a genetic algorithm (GA). First, a Matlab model of the FPA...
Joachim Becker, Stanis Trendelenburg, Fabian Henri...