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ASAP
2003
IEEE
153views Hardware» more  ASAP 2003»
15 years 3 months ago
Hardware Synthesis for Multi-Dimensional Time
This paper introduces basic principles for extending the classical systolic synthesis methodology to multi-dimensional time. Multi-dimensional scheduling enables complex algorithm...
Anne-Claire Guillou, Patrice Quinton, Tanguy Risse...
CGI
2003
IEEE
15 years 3 months ago
Hardware Assisted Multichannel Volume Rendering
We explore real time volume rendering of multichannel data for volumes with color and multi-modal information. We demonstrate volume rendering of the Visible Human Male color data...
Abhijeet Ghosh, Poojan Prabhu, Arie E. Kaufman, Kl...
DATE
2002
IEEE
161views Hardware» more  DATE 2002»
15 years 3 months ago
Hardware/Software Trade-Offs for Advanced 3G Channel Coding
Third generation’s wireless communications systems comprise advanced signal processing algorithms that increase the computational requirements more than ten-fold over 2G’s sys...
Heiko Michel, Alexander Worm, Norbert Wehn, Michae...
FCCM
2000
IEEE
103views VLSI» more  FCCM 2000»
15 years 3 months ago
A Networked FPGA-Based Hardware Implementation of a Neural Network Application
This paper describes a networked FPGA-based implementation of the FAST (Flexible Adaptable-Size Topology) architecture, a Arti cial Neural Network (ANN) that dynamically adapts it...
Héctor Fabio Restrepo, Ralph Hoffmann, Andr...
DNA
2007
Springer
106views Bioinformatics» more  DNA 2007»
15 years 2 months ago
Hardware Acceleration for Thermodynamic Constrained DNA Code Generation
Reliable DNA computing requires a large pool of oligonucleotides that do not produce cross-hybridize. In this paper, we present a transformed algorithm to calculate the maximum wei...
Qinru Qiu, Prakash Mukre, Morgan Bishop, Daniel J....