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CODES
2006
IEEE
15 years 2 months ago
Increasing hardware efficiency with multifunction loop accelerators
To meet the conflicting goals of high-performance low-cost embedded systems, critical application loop nests are commonly executed on specialized hardware accelerators. These loop...
Kevin Fan, Manjunath Kudlur, Hyunchul Park, Scott ...
ASAP
2000
IEEE
102views Hardware» more  ASAP 2000»
15 years 2 months ago
A Theory for Software-Hardware Co-Scheduling for ASIPs and Embedded Processors
Exploiting instruction-level parallelism (ILP) is extremely important for achieving high performance in application specific instruction set processors (ASIPs) and embedded proces...
Ramaswamy Govindarajan, Erik R. Altman, Guang R. G...
FPL
2000
Springer
93views Hardware» more  FPL 2000»
15 years 2 months ago
Reconfigurable Computing between Classifications and Metrics - The Approach of Space/Time-Scheduling
Abstract. Reconfigurable computing receives its merits from scheduling timebased into space-based execution. This paper reviews some common parameters and introduces an additional ...
Christian Siemers
ICNP
2009
IEEE
15 years 5 months ago
Better by a HAIR: Hardware-Amenable Internet Routing
—Routing protocols are implemented in the form of software running on a general-purpose microprocessor. However, conventional software-based router architectures face significan...
Firat Kiyak, Brent Mochizuki, Eric Keller, Matthew...
FCCM
2006
IEEE
100views VLSI» more  FCCM 2006»
15 years 4 months ago
Enabling a Uniform Programming Model Across the Software/Hardware Boundary
In this paper, we present hthreads, a unifying programming model for specifying application threads running within a hybrid CPU/FPGA system. Threads are specified from a single p...
Erik Anderson, Jason Agron, Wesley Peck, Jim Steve...